This invention relates to methods of manufacturing large crystalline and monocrystalline semiconductor-on-insulator, conductor-on-insulator and superconductor-on insulator composites, and integrated circuits utilizing such composites.
Large, high quality gallium arsenide and other III-V and II-VI semiconductor substrates for applications such as active and passive optical devices, microwave, millimeter wave devices, millimeter wave integrated circuits, and high speed digital signal processing applications, which have good mechanical strength and thermal properties are needed to realize the performance potential for such materials. However, the brittle nature, thermal volatility and susceptibility of such materials to processing damage from cutting, polishing or prolonged exposure to high temperature, as well as relatively high bulk defect densities, present significant limitations to development of technologies using such materials.
Because of the developed technology for manufacture and processing of large diameter monocrystalline silicon wafers, and the desirable.mechanical and thermal properties of silicon, substantial effort has been directed to the development methods for epitaxial growth of GaAs on monocrystalline silicon wafers [e.g., Fischer, R., et al., "Prospects for the Monolithic Integration of GaAs and Si", IEEE Gallium Arsenide Integrated Circuit Symposium, Monterey, Calif., Nov. 12-14, 1985, IEEE, New York, USA, 210 pp. pp. 71-3, 1985; Fischer, R., et al., "GaAs Biopolar Transistors Grown on (100) Si Substrates by Molecular Beam Epitaxy", Appl. Phys. Lett. Vol. 47, No. 4, pp. 397-399,Aug. 15, 1985]. However, the large lattice mismatch produces a high density of dislocations which adversely affect the properties of the GaAs layer. This problem has been partially alleviated by the use of silicon wafer substrates which are precisely "tilted" at a small angle from the 100 crystalline surface. Such "tilting" of the silicon wafer substrate creates a series of "steps" at the GaAs-Si interface, creating edge dislocations with Burgers vectors parallel to the interface so that they do not propagate into the bulk epitaxial layer, which reduce the dislocation density [Fischer, R., et al., "Dislocation Reduction in Expitaxial GaAs on Si (100)", Appl. Phys. Lett., Vol. 48, No. 18, pp. 1223-1225, May 5, 1986]. The incorporation of an InGaAs/GaAs strained-layer superlattice in GaAs-on-silicon composites may also be used to significantly reduce the density of (e.g., threading) dislocations in thick GaAs layers above the strained layer superlattice [Fischer, R., et al., supra]. However, the growth of thick epitaxial layers of GaAs and strained-layer superlattice structures is expensive, time consuming and unsuited to high volume production. In addition, because the epitaxial GaAs layers are directly contiguous to the semiconductive silicon wafer substrate, circuit elements made from such wafers may have higher capacitance than desirable to fully utilize the potential speed of the GaAs layer, and may have undesirably low resistance to ionizing radiation.
There has also been substantial research effort directed to the growth of device-worthy silicon crystals on insulating substrates, to provide latch-up free integrated circuits having low sensitivity to ionizing radiation, low capacitance, and high packing density for very large scale IC's [Leamy, et al., "Laser Fabrication of Silicon on Dielectric Substrates" Proceedings of the Materials Research Society Annual Meeting, Boston, Mass., Nov. 16-19, 1981, North- Holland, Amsterdam, Netherlands, pp. 459-504, 1982]. Typically, polysilicon or amorphous silicon is recrystallized laterally on a layer of silicon dioxide through contact windows to the monocrystalline silicon wafer substrate. Such recrystallization has been accomplished by laser beam scanning to selectively melt and recrystallize the silicon surface layer, by the application of halogen lamps in a scanning arrangement to melt the silicon layer for recrystallization without melting the wafer substrate, or by programmed application of halogen lamps to the entire wafer over an extended time period to melt the surface while cooling the wafer substrate below the melting point of silicon. Very close control of the temperature profile is a crucial parameter in such processes. [See e.g., J. P. Colinge, et al., "Use of Selective Annealing for Growing Very Large Grain Silcon-On-Insulator", Applied Physics Letters, Vol. 41, No. 14, pp. 346-347, August, 1982; J. P. Colinge, et al., "Transistors Made in Single-Crystal SOI Films", IEEE Electron Device Letters, Vol. EDL-4, No. 4, April, 1983; G. K. Celler, et al., "Seeded Oscillatory Growth of Si over SiO2 by CW Laser Irradiation", Applied Physics Letters, Vol. 40, No. 12, June, 1983; CM. Kyung, "Temperature Profile of a Silicon-On-Insulator Multilayer Structure in Silicon Recrystallization with Incoherent Light Source", IEEE Trans. Electron Devices, Vol. ED-31, No. 12, pp. 1845-1851, Dec. 1984; T. Stultz, et al., "Beam Processing of Silicon with a Scanning CW Hg Lamp", Elsevier, N.Y., pp. d463-76, 1983; D. Bensahel, et al., "Localization of Defects on SOI Films via Selective Recrystallization Using Halogen Lamps", Electron Lett., Vol. 19, No. 13, pp. 464-466, Jun. 23, 1983; H. J. Leamy, et al., "Laser Fabrication of Silicon on Dielectric Substrates" Proceedings of the Materials Research Society Annual Meeting, Boston, Mass., Nov. 16-19, 1981, North-Holland, Amsterdam, Netherlands, pp. 459-504, 1982]. However, these techniques have various disadvantages in terms of cost, production capacity and/or device properties or quality. For example, laser scanning techniques are costly and present difficulty in obtaining high quality single crystal silicon near the edges of the beam. In addition, overlapped successive scans can destroy the single crystal produced by the earlier scans causing random nucleation in the overlap region. Scanning or relatively slow heating of the amorphous silicon layer by means of halogen lamps tends to cause warping of the wafers, induces stress and imperfections in the recrystallized materials and permits impurity diffusion.
Moreover, such techniques have not been successfully applied to GaAs on insulator wafer production to produce high quality III-V devices. The development of a potentially high volume, inexpensive method for the formation of large area monocrystalline GaAs wafers would meet a significant need for the realization of the high speed potential of III-V large scale integrated circuits. Such methods and devices which provide for waveguide optical coupling of active optical diode and laser circuit elements would also be desirable. Methods and apparatus for backside gettering of impurities, and for optically pattern-controlled application of pulsed optical energy would also be desirable.
Accordingly, it is an object of the present invention to provide improved methods for manufacturing monocrystalline seeded semiconductor-on-insulator devices and structures, as well as the devices and structures themselves. It is a further object to provide economical methods for producing highly crystalline semiconductor surfaces for large area use such as solar power cells. It is a further object to provide improved integrated circuit and other semiconductor electronic devices. These and other objects will be apparent from the following drawings and description.